Biren Technology BR106 / BR110 / BR166 — Domestic Chinese GPGPU Family

Specifications

Overview

Biren Technology, founded in 2019, has consolidated its accelerator business onto one proprietary GPGPU architecture that now spans data-centre training, inference and edge computing. The current production generation — BR106, BR110 and BR166 — has completed research, tape-out and mass production, and the same architecture also covers PCIe cards, OAM modules, servers and full cluster reference designs.

The family is built on 2.5D chiplet packaging with a dual-compute-die design, an approach Biren credits with advantages in performance scalability, energy efficiency and manufacturing yield. The original flagship, BR100, put 77 billion transistors on a 7 nm process with 64 GB of HBM2E on a 4,096-bit interface at 1.64 TB/s, rated at 256 FP32 TFLOPS, 512 TF32 TFLOPS, 1,024 BF16 TFLOPS and 2 INT8 PFLOPS in an OAM module of up to 550 W. The BR104 halves most of those figures into a 300 W FHFL dual-wide PCIe Gen5 card with 32 GB of HBM2E at 819 GB/s, PCIe Gen5 x16 with CXL support and BLink interconnect at 192 GB/s across three x8 ports.

Software is central to the strategy. The Birensupa platform covers programming models, compilers, acceleration libraries, training and inference frameworks and developer toolchains in a single stack, and is compatible with mainline frameworks including PyTorch and vLLM as well as major Chinese large models such as DeepSeek, StepFun, Tencent Hunyuan, Zhipu GLM, Alibaba Qwen and Kimi. Above the card level, the LightSphere X supernode solution targets linear scaling efficiency across large GPU clusters, and Biren reports thousand-card-scale deployments with telecom operators and national computing platforms. Commercially the company listed on the Hong Kong Stock Exchange in January 2026 and grew first-half 2026 revenue to $183.9 million, with the BR20X generation moving toward commercialisation ahead of BR30X and BR31X.

Key Benefits

One architecture across training, inference and edge so software investment carries between product tiers; 2.5D chiplet design for yield and scalability advantages; mature domestic software with PyTorch and vLLM compatibility plus support for DeepSeek, Qwen, GLM and Hunyuan models; proven cluster deployments at thousand-card scale; and a published multi-generation roadmap from BR106/BR110/BR166 through BR20X, BR30X and BR31X.

Applications

Domestic AI data-centre training and inference; large language model serving; search and recommendation acceleration; national intelligent-computing centre builds; telecom operator AI platforms; and edge inference deployments using the lower-power members of the family.

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