Specifications
Family
AMD Xilinx Virtex UltraScale+ (16 nm)
Device
XCVU9P
MPNs (package / speed variants)
XCVU9P-1FLGA2104E (-1FLGA2104I) · XCVU9P-2FLGA2104E (-2FLGA2104I) · XCVU9P-2FLGA2577E · XCVU9P-3FLGA2104E
Process
16 nm FinFET (TSMC 16FF+)
System Logic Cells
2,586,000
CLB Flip-Flops
2,364,960
DSP Slices
6,840 × DSP48E2
Block RAM
75.9 Mb (2,109 × 36 Kb blocks)
UltraRAM
360 Mb in 960 blocks — single-cycle SRAM-class storage density
Transceivers
120 × GTY, up to 32.75 Gb/s
PCI Express
Integrated PCIe Gen3 x16 blocks with DMA-capable integrated block for PCIe
Ethernet
Integrated 100G Ethernet MAC with PCS/PMA × 2, plus 150G Interlaken
Memory Interface
DDR4-2666 hard memory controllers; up to 8 controllers
Configuration
SRAM-based with AES-GCM-256 bitstream encryption and RSA-4096 authentication
Packages
FLGA2104, FLGA2577, FSGD2104
Speed Grades
-1, -2, -3 and low-power L variants
Temperature Grades
E and I, plus defence-grade Q options
Power
Programmable 0.85 V core with voltage scaling; -L devices for lowest static power
Target Use
400G networking, datacenter SmartNIC and compute acceleration, radar, ASIC emulation, genomic sequencing
Overview
The Virtex UltraScale+ XCVU9P is a 16 nm datacenter-class FPGA: 2,586,000 system logic cells, 6,840 DSP48E2 slices, 75.9 Mb of block RAM and an additional 360 Mb of UltraRAM, which behaves as single-cycle SRAM with much higher density than conventional block RAM.
Its 120 GTY transceivers at 32.75 Gb/s and two integrated 100G Ethernet MACs make it a natural fit for 400G line cards, SmartNIC datapaths and compute-acceleration cards, while the UltraRAM capacity lets on-chip tables and buffers grow without consuming fabric block RAM.
Key Benefits
UltraRAM adds 360 Mb of SRAM-class on-chip storage that frees block RAM for FIFOs and control. 120 × 32.75 Gb/s GTY lanes plus two 100G MACs enable 400G-class datapaths in a single device. AES-GCM-256 encryption and RSA-4096 authentication for bitstream IP protection.
Applications
400G/800G networking line cards, datacenter SmartNICs and compute offload, ASIC and SoC emulation, phased-array radar, genomic and financial acceleration, and professional broadcast switching.
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