AMD VCK5000 Versal AI Core Development Card — 145 TOPS INT8 Inference Accelerator

Specifications

Overview

The AMD VCK5000 is the development-card implementation of the Versal AI Core series, built on the 7 nm VC1902 adaptive SoC. What separates it from a conventional FPGA accelerator card is which engine does the maths: the work runs on 400 Versal AI Engines, a vector VLIW array designed for the dense multiply-accumulate patterns inside neural networks, not on the programmable logic fabric.

That architectural choice changes the development flow. AI Engine kernels are written in C/C++ and built with Vitis and Vitis AI, so a team that has trained a model in TensorFlow or PyTorch can move it to the card through a software toolchain rather than hand-writing RTL. Partner stacks extend the reach further: Mipsology Zebra exposes the card as a drop-in inference accelerator for existing model-serving code, and Aupera VMSS targets video-AI pipelines.

AMD publishes up to 145 TOPS INT8, 37 TOPS INT16 and 12 TFLOPS FP32 for the board. Those figures are relevant against the power envelope: the card sits in the sub-100 W class, and the published comparison against a 92 W FPGA alternative frames the VCK5000 around inference efficiency per watt rather than peak throughput.

The VC1902 device also includes dual Arm Cortex-A72 and dual Cortex-R5F scalar engines plus 1,968 DSP58 engines and roughly 899K logic cells, so the same card can host the control plane, the fixed-function DSP path and the neural network inference in one device. Applications named by AMD include 5G, data-centre compute, AI, signal processing and radar.

Key Benefits

145 TOPS INT8 on AI Engines: neural-network throughput in a sub-100 W PCIe card. C/C++ software flow: Vitis and Vitis AI instead of hand-written RTL. Drop-in partner stacks: Mipsology Zebra and Aupera VMSS for inference and video AI. Heterogeneous device: scalar Arm cores, DSP58 engines and adaptable logic on one VC1902 die.

Applications

CNN/RNN/NLP inference acceleration, video-AI and computer-vision pipelines, 5G physical-layer processing, radar and signal processing, and data-centre inference offload where efficiency per watt dominates.

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