Specifications
Device Type
Custom sensor-fusion ASIC, internally called carTPU
Process Node
5 nm (N5), with 208 mm2 of silicon
Package
45 mm x 45 mm FCBGA
INT8 Compute
160 TOPS (INT8 x INT8)
FP16 Compute
80 TFLOPS
On-chip SRAM
64 MB
Register File
8 MB
In-package Memory
LPDDR5x at 273 GB/s
External Memory Bandwidth
160 GB/s
Host Interface
PCIe Gen 5 x8
Networking
25G Ethernet
Thermal Envelope
Under 75 W TDP
Compute Backbones
Three — camera, radar and fusion; the fusion path is latency-critical while camera and radar run at maximum concurrency
Precision Strategy
Higher-precision integer and FP16 paths to preserve perception fidelity, plus temporal denoising for low-light perception
Vehicle Context
Part of the sixth-generation Waymo Driver compute stack, which quotes over 1,000 TOPS of ML performance across its ASICs
Disclosed
August 20, 2026, with an architecture talk at Hot Chips 2026 on 24 August
Overview
The Waymo carTPU is the custom silicon at the centre of the sixth-generation Waymo Driver. Rather than pushing raw throughput, Waymo optimised for fidelity and latency: 160 TOPS of INT8 and 80 TFLOPS of FP16, paired with 64 MB of on-chip SRAM, an 8 MB register file and LPDDR5x memory stacked in-package at 273 GB/s.
The chip is deliberately compact for its class — 208 mm2 of silicon on a 5 nm process inside a 45 mm x 45 mm FCBGA package, with a PCIe Gen 5 x8 host link, 25G Ethernet and a thermal design under 75 W. Waymo expresses a clear preference for higher numerical precision than accelerator-class hardware, alongside dedicated temporal denoising so perception holds up in low light.
Architecturally the carTPU splits into three backbones: camera, radar and fusion. Camera and radar run at maximum concurrency while the fusion path is held latency-critical, feeding an inference engine that runs sensor-fusion ML models. Waymo disclosed the design on 20 August 2026 and presented it at Hot Chips 2026, in the context of a sixth-generation Driver quoting over 1,000 TOPS of ML performance across its ASIC set. QS Compute supplies edge AI accelerators, embedded vision compute and automotive-grade processing hardware — get in touch for a quote.
Key Benefits
Safety-first precision: dedicated INT8 and FP16 paths instead of aggressive low-precision only. Latency-controlled fusion: separate camera, radar and fusion backbones. Compact and cool: 45 mm package under 75 W. Automotive-grade integration: in-package LPDDR5x, PCIe Gen 5 and 25G Ethernet.
Applications
Autonomous vehicle perception and sensor fusion, ADAS domain controllers, robotics perception stacks, embedded multi-sensor inference, and safety-critical edge AI where precision and deterministic latency matter more than peak TOPS.
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