Specifications
Product
Mythic M1076 Analog Matrix Processor (AMP), second product in the M1000 series after the M1108
Architecture
Array of 76 Mythic AMP tiles, each with a Mythic Analog Compute Engine (Mythic ACE)
Compute
Up to 25 TOPS per chip
Weight Capacity
Up to 80 million DNN weight parameters stored on chip
External Memory
None required - model parameters are stored and executed entirely on chip
Key Benefit
Eliminates the memory bandwidth bottleneck of digital accelerators by computing in place
Power
3 to 4 W running typical complex models; roughly 10x lower power than comparable digital solutions
Process Advantage
Up to 100x system-level performance per watt per dollar versus conventional digital or GPU inference (vendor claim)
Interface
4-lane PCIe 2.1, 4 Gb/s per lane, up to 2 GB/s bandwidth
Additional IO
GPIO, QSPI, I2C and UART
Package
19 x 15.5 mm BGA
Precision
INT4 and INT8 operations
Temperature
-40 C to +85 C junction operating temperature
Execution
Multiple DNNs run concurrently; deterministic and predictable execution for real-time systems
M.2 Module MM1076
M.2 M-key 22 x 80 mm card with one M1076, 4-lane PCIe 2.1, 2 GB/s
M.2 Module ME1076
M.2 A+E key 22 x 30 mm card with one M1076, 2-lane PCIe 2.1, 1 GB/s, for space-constrained designs
PCIe Card MP10304
Half-height half-length PCIe card with four M1076s - up to 100 TOPS, up to 320 million weights, under 25 W
Scaling
Single chip up to a 16-chip PCIe card delivering up to 400 TOPS and 1.28 billion weights at 75 W
Software
Supports models built in PyTorch, Caffe and TensorFlow; quantisation from FP32 to INT8, retraining for the ACE and graph compilation; pre-qualified models available
Target Applications
Industrial machine vision, autonomous drones, surveillance cameras, network video recorders, AR and VR with low-latency pose estimation, smart city and enterprise edge
Cross-Brand
Hailo-8 and Hailo-10H, Kinara Ara-2, MemryX MX3, BrainChip Akida, DEEPX DX-M1
Overview
Mythic's Analog Matrix Processor takes a different route to edge inference. Instead of moving weights from DRAM to a digital MAC array on every inference, the M1076 stores the weights inside flash memory and performs the matrix multiplication in the analog domain directly where the data is held. The result is a chip that needs no external DRAM at all.
That architecture is why the numbers look unusual: up to 25 TOPS in a single chip running typical complex models at 3 to 4 W, with up to 80 million weight parameters resident on chip. Because there is no memory traffic to schedule, execution is deterministic, which suits real-time vision pipelines where worst-case latency matters more than average throughput.
Deployment is deliberately familiar. The MM1076 is a 22 x 80 mm M.2 M-key card and the ME1076 is a 22 x 30 mm A+E key card for tighter enclosures, while the MP10304 half-height half-length PCIe card carries four AMPs for up to 100 TOPS under 25 W. At the top of the range a 16-chip card reaches 400 TOPS and 1.28 billion weights at 75 W.
Key Benefits
No external DRAM removes the dominant energy cost of inference, 3 to 4 W for up to 25 TOPS suits passively cooled enclosures, and deterministic execution gives predictable real-time latency for vision systems.
Applications
Industrial machine vision, autonomous drone perception, surveillance cameras and network video recorders, AR and VR low-latency pose estimation, smart city sensing, and enterprise edge inference where thermal and power budgets are fixed.
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