Specifications
Part
InferX X1 edge inference accelerator (card and IP)
Architecture
nnMAX dynamic tensor processor array, 2x2 tile configuration plus a 1x1 EFLX eFPGA block
Tiles
4 nnMAX tiles, approx. 2.1 TOPS each
Total Throughput
8.4 TOPS (integer inference)
Process
TSMC 16 nm
MAC Units
4K MAC units
On-Chip SRAM
12 MB
External Memory
Single LPDDR4 DRAM for weights/activations
Host Interface
PCIe Gen3 / Gen4
Host Architectures
x86 or Arm, multiple operating systems
Card Form Factor
PCIe half-height card (approx. US$399 list)
Variant
InferX X1M module for embedded integration
Status
nnMAX IP continues under Analog Devices (acquired Flex Logix, Nov 2024)
Overview
The Flex Logix InferX X1 is an edge AI inference accelerator built on the company's nnMAX reconfigurable tensor architecture. A single X1 chip arrays four nnMAX tiles in a 2x2 configuration — roughly 2.1 TOPS each, for 8.4 TOPS total — alongside a 1x1 EFLX eFPGA block, fabricated on TSMC 16 nm.
The design pairs 4K MAC units with 12 MB of on-chip SRAM and needs only a single external LPDDR4 DRAM, which keeps board area and power low while sustaining high MAC utilisation. It connects to an x86 or Arm host over PCIe Gen3/Gen4 and was offered as an approximately US$399 half-height PCIe card plus an X1M embedded module. The nnMAX architecture scales to NxN tile arrays without GDS changes, and continues to be licensed following Analog Devices' acquisition of Flex Logix in November 2024.
Key Benefits
8.4 TOPS across four nnMAX tiles on 16 nm · 4K MAC units with 12 MB on-chip SRAM · single external LPDDR4 DRAM keeps BOM low · PCIe Gen3/Gen4 to x86 or Arm hosts · architecture scales to 100+ TOPS.
Applications
Real-time high-resolution vision inference at the edge, multi-camera analytics, industrial inspection, smart-city and retail video analysis, and sensor-fusion workloads where a low-power PCIe accelerator is preferred over a datacentre GPU.
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