Specifications
Product
DEEPX DX-M1+
Type
Multi-chip M.2 AI accelerator module
Configurations
Dual-chip 50 TOPS · Quad-chip 100 TOPS
Base Silicon
DEEPX DX-M1 NPU (25 TOPS INT8 per chip)
AI Performance
50 TOPS (2 chips) or 100 TOPS (4 chips)
Video Option
Dual-chip variant pairs 2 NPU chips with 2 Rockchip SoCs for transcode / decode
Video Capability
H.264 / H.265 encode and decode on the transcoding variant
Form Factor
M.2 module (2230/2242/2280 family)
Framework Support
TensorFlow, ONNX, Keras, PyTorch via DX-COM compiler
Compiler / SDK
DXNN SDK (DEEPX)
Efficiency Class
DX-M1 architecture — 1–5 W per NPU chip
Storage Integration
Apacer 4 TB PCIe SSD + 2 × DX-M1 co-packaged on a single M.2 board
Cooling
Heatsink required on multi-chip configurations
OS Support
Windows 11/10, Debian-based Linux, Yocto
Target Applications
Multi-camera video analytics, smart city, industrial inspection, robotics
Scaling
Same host interface as DX-M1 — add chips instead of adding cards
Compliance
RoHS
Lead Time
4–6 weeks
MOQ
1 unit
Overview
The DEEPX DX-M1+ answers the question of what to do when one 25 TOPS edge module is not enough but a discrete accelerator card will not fit. It stacks two or four DX-M1 NPU chips on a single M.2 board, yielding 50 TOPS or 100 TOPS through the same host interface.
The dual-chip transcoding variant is the more interesting configuration for video workloads: it pairs two NPU chips with two Rockchip SoCs, so the module can simultaneously decode high-channel-count camera streams and run inference on them — the ratio real multi-camera analytics boxes need.
DEEPX has also demonstrated co-packaging a 4 TB PCIe SSD with two DX-M1 processors on one M.2 board, collapsing storage and inference into a single slot.
Key Benefits
50 or 100 TOPS from one M.2 slot by stacking NPU chips; integrated video transcode on the dual-chip variant (2 × NPU + 2 × Rockchip); DXNN SDK compatibility with single-chip DX-M1; scales by chip count rather than card count.
Applications
High-channel-count video analytics servers, smart-city camera aggregation, industrial multi-line visual inspection, robotics perception stacks, and edge NVR appliances needing simultaneous decode and inference.
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