Specifications
Accelerator Type
Standalone CVflow AI co-processor — Ambarella's first dedicated AI accelerator chip
Compute Engine
Third-generation CVflow computer vision and deep learning processor
Host Interface
PCIe Gen 3 x1 or USB 3.2 — appears to the host as a standard PCIe device
Power Envelope
2 W to 5 W in current customer designs
Network Support
CNNs, vision transformers, multimodal transformers and hybrid networks
Reference Design
XCalibur — X7 paired with LPDDR5 memory on a 2280 M.2 card
PCIe Throughput
Above 840 MB/s in the XCalibur M.2 reference design
Concurrency
Enough throughput for several concurrent video streams and models
On-card Memory
LPDDR5 on the XCalibur M.2 reference design
Form Factor
Discrete accelerator chip; M.2 2280 card in the reference design
Software Stack
Cooper Developer Platform and Cooper Model Garden for model deployment and tooling
Migration Path
Same CVflow architecture as Ambarella AI SoCs — perception pipelines move across without a software rewrite
Host Support
Arm and x86 host processors
Design Wins
Leading OEMs in several key verticals are currently creating designs with X7
Target Applications
Retail and physical security, industrial inspection, mobile robots, transportation infrastructure
Related SoC Family
Ambarella N1-655 and CV7 edge AI vision SoCs share the CVflow engine
Announced
September 15, 2026 — Santa Clara, California
Overview
The Ambarella X7 is a standalone edge AI accelerator that brings the company's third-generation CVflow engine to systems that were never designed around an AI SoC. Rather than replacing the host processor, X7 attaches over a single PCIe Gen 3 lane or USB 3.2 and presents itself as a standard PCIe device, so an existing Arm or x86 platform gains AI inference capability without a board redesign, enclosure change or bill-of-materials increase.
Because X7 runs the same CVflow architecture Ambarella integrates into more than 50 million shipped AI SoCs, a perception pipeline already ported to an Ambarella SoC can be moved to X7 without a software rewrite. It supports CNNs, vision transformers, multimodal transformers and hybrid networks, and pairs with the Cooper Developer Platform and Model Garden for deployment tooling. The XCalibur reference design packages X7 with LPDDR5 memory on a 2280 M.2 card at above 840 MB/s of PCIe throughput, targeting retail and physical security, industrial inspection, mobile robots and transportation infrastructure.
Key Benefits
Retrofit AI capability: add or expand inference on an existing Arm or x86 host without redesigning the platform. Low power: 2-5 W operation suits fanless and enclosed industrial systems. Transformer-ready: CNN, ViT, multimodal and hybrid network support. One-lane simplicity: a single PCIe Gen 3 lane or USB 3.2 link is enough. Familiar tooling: Cooper Developer Platform and Model Garden, with source-level portability from Ambarella SoCs.
Applications
Edge video analytics and physical security appliances, industrial machine-vision inspection stations, autonomous mobile robots and AGVs, transportation and smart-infrastructure monitoring, retail loss-prevention and traffic analytics, and any legacy Arm or x86 system that must gain modern AI inference without a platform redesign.
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